最低学历：硕士

工作经验：5-10年

职位类型：全职

验证工程师（工作地点可选合肥/上海）

Position Description: 

Deliver and implement advanced verification solution by utilizing Synopsys Verification product portfolio. The engineers need to act as a strong team member and contributor. Exercise judgment within generally defined practices and policies. Specific responsibilities include: Deep understanding on ASIC design and verification flow. Excellent knowledge of advanced verification methodology. Good in System Verilog, System C and using Verification components (VIP). Experienced on developing and using assertion based verification and formal analysis method. Skilled in scripting language like Perl, C shell, Python, Makefile.

Position Requirement:

Must have BS degree with 5+ years of applicable experience, MS degree with 3+ years of applicable experience in microelectronics, electrical engineering. Essential that the candidate demonstrates strong communication skill. Have demonstrated successful completion of 6+ design projects as an individual contributor. Demonstrated hands on experience and expertise with EDA verification tools, flow and methodologies required to execute verification projects. Need to demonstrate successful completion of 3+ verification projects as individual contributor. Memory IP project verification experience is preferred.

职位描述：              
DELIVER和实施先进的验证方案验证城市利用Synopsys公司的产品组合。《工程师需要的行为作为一个强大的团队成员和contributor。法院判决的一般定义在运动实践和政策。具体责任包括：深的理解在ASIC设计和验证流程。优秀大学的先进知识的验证方法。好的Verilog的系统，系统采用C和核查零件（VIP）。治疗对开发和利用assertion推理和分析方法验证的目的。在skilled脚本语言像Perl，Python，C壳，makefile。
职位要求：              
必须具有理学学士学位，5年以上相关工作经验，理学硕士学位，3年以上微电子、电气工程相关工作经验。应聘者必须具备很强的沟通能力。以个人贡献者的身份成功完成了6个以上的设计项目。在执行验证项目所需的EDA验证工具、流程和方法方面具有实践经验和专业知识。需要证明作为个人贡献者成功完成了3+个验证项目。有内存IP项目验证经验者优先。