最低学历：硕士

工作经验：5-10年

职位类型：全职

数字设计工程师（工作地点合肥/上海）

Position Description:

Focus on high speed interface IP design/implementation. The engineers need to act as a strong team member and contributor. Exercise judgment within generally defined practices and policies. Specific responsibility include: Proficiency in logic design, simulation Proficiency in Verilog and simulation environment. Good knowledge of IC design. At least five year experience working on digital IC development projects, excellent communication skills and the uncanny ability to both lead and contribute in a cooperative team environment.

Position Requirement:

Must have BS degree with 5+ years of applicable experience, MS degree with 3+ years of applicable experience in microelectronics, electrical engineering. Essential that the candidate demonstrates strong communication skill. Have demonstrated successful completion of 6+ design projects as an individual contributor. Familiar with one or more interface IP protocol including JEDEC-DDR, HBM, PCIE, USB, GDDR6 etc. and have memory IP project design experience is preferred.

职位描述：              
高速接口IP设计。作为一个工程师需要强壮的队员和在一般的做法，与判断运动定义的政策。具体责任包括：熟练精通Verilog仿真逻辑设计和仿真环境。IC设计的良好知识。至少五年工作经验的数字IC的开发项目，优秀的通信技能和能力都有助于uncanny牵头和合作在团队环境。
职位要求：              
必须具有理学学士学位，5年以上相关工作经验，理学硕士学位，3年以上微电子、电气工程相关工作经验。应聘者必须具备很强的沟通能力。以个人贡献者的身份成功完成了6个以上的设计项目。熟悉一个或多个接口IP协议，包括jedec-ddr、hbm、pcie、usb、gddr6等，有内存IP项目设计经验者优先。